1. Field of the Invention
The present invention relates to a semiconductor memory having a memory cell of DRAM and an interface of SRAM.
2. Description of the Related Art
In recent years, a semiconductor memory called a pseudo SRAM (Pseudo-SRAM) has been developed. The pseudo SRAM has a memory cell of DRAM (dynamic memory cell) and operates as a SRAM carrying out a refresh operation of the memory cell internally and automatically. The dynamic memory cell used in the pseudo SRAM has a small area. For this reason, a large capacity pseudo SRAM with a low bit cost can be developed.
The pseudo SRAM has an interface of SRAM. In synchronization with an access command, an address is received at once and a write access operation and a read access operation are carried out. A controller which accesses the pseudo SRAM needs to inactivate a chip enable signal each time the address is changed. Therefore, the pseudo SRAM can not carry out the write access operation or the read access operation continuously while a part of the address is held. For this reason, especially when memory cells are sequentially accessed using continuing addresses, the data transfer rate will decrease.
On the other hand, there is proposed a pseudo SRAM which carries out so called a page operation in response to a dedicated control signal when the memory cells are sequentially accessed using continuing addresses in the pseudo SRAM (e.g., Japanese Unexamined Patent Application No. 2004-259318). Here, the page operation is an operation of writing data to a memory cell sequentially or an operation of reading data from a memory cell sequentially by changing only column address while a word line is activated. By carrying out the page operation, the operation efficiency of the pseudo SRAM is improved and the data transfer rate is increased.
However, when carrying out the page operation using a dedicated control signal, a controller which accesses the pseudo SRAM needs to output the dedicated control signal. This does not allow the conventional controller to be used, and a dedicated controller needs to be developed for the pseudo SRAM capable of carrying out the page operation. As a result, the cost of a system incorporating the semiconductor memory will increase.